1. Field of the Invention
The present invention relates to a data processing apparatus, a data processing method and a recording medium, more particularly to a technology suitable for use in reducing power consumption.
2. Description of the Related Art
Conventionally, there has been known a technology for reducing power consumption by stopping clock supply to a given functional module when the functional module is not in use (e.g., Japanese Patent Application Laid-Open No. 6-202754). On the other hand, also when the functional module is in use, by stopping the clock supply to the functional module corresponding to a clock control request signal, a higher power consumption effect can be achieved.
However, if the supply of clock is stopped suddenly during use of the functional module, matching in data transfer between input and output to/from the module might not be maintained, which may induce a malfunction. Japanese Patent Application Laid-Open No. 2003-58271 discusses a technology for stopping clock during use while avoiding such a malfunction. The technology discussed by Japanese Patent Application Laid-Open No. 2003-58271 includes a clock generation unit, a first module for asserting a clock control request signal and a plurality of second modules which respond to the clock control request signal and assert a clock control acknowledge signal. The second module responds to an asserted clock control request signal and after a processing being currently executed terminates, stops a subsequent processing and asserts the clock control acknowledge signal. When all the clock control acknowledge signals from one or plural second modules are asserted, the clock generation unit changes clocks supplied to the second module selectively.
When a processing being currently executed terminates after a request for stopping the clock is dispatched, the technology discussed by Japanese Patent Application Laid-Open No. 2003-58271 takes a procedure of stopping a subsequent processing and sending back the acknowledge signal. Thus, execution of this procedure takes much time depending on the content of a processing being currently executed. When it is intended to stop the clock delicately during an operation of the functional module, the time required for the execution of the procedure discussed in Japanese Patent Application Laid-Open No. 2003-58271 restricts the lower limit of a clock down period, whereby keeping the power saving effect on a low level.